The present invention relates to a technique for measuring geometry of a fine pattern on the surface of a sample (a semiconductor wafer, a reticle, etc.) and its dimensions.
Currently, the use of a critical-dimension scanning electron microscope (hereinafter abbreviated to as CD-SEM) is a mainstream in measuring dimensions of a semiconductor device pattern. The structure of the CD-SEM is fundamentally the same as that of the scanning electron microscope. First, electrons emitted from an electron source of a heating type or field emission type are accelerated. Subsequently, an electron beam is converged in diameter by a lens to form a focused electron beam. Then, the electron beam is scanned on a sample (e.g., a wafer, a reticle, etc.) and generated secondary electrons are detected, whereby a two-dimensional scanning electron image of the fine pattern on the sample can be obtained. In doing this, if the primary electrons scanned on the sample have larger landing energies, a generation efficiency of the secondary electrons becomes smaller than unity, and accordingly the sample will tend to be charged up. Therefore, it is required that landing energy should be made as small as possible. Moreover, since materials that are newly introduced into a process include ones that are weak against the electron beam, it is mandatory to lower the energy of incident electrons in this respect. However, this requirement conflicts with achievement of higher resolution of the CD-SEM demanded along with miniaturization of a circuit pattern. Therefore, a metrology system is equipped with a mechanism whereby an accelerating voltage after generation of electrons from the electron source is set somewhat higher and subsequently a deceleration voltage is impressed on the electrons (impression of a retarding voltage) before the electrons are incident on the sample. With this mechanism, the metrology system can realize compatibility between higher resolution of an obtained image and reduction in charge-up of the sample.
However, in recent years, some samples with charge-up have begun to exist among samples under measurement. It is discovered that the charge-up of the sample and its distribution cause focusing error, astigmatism, etc. of the CD-SEM. Causes of charged-up samples are considered to lie in plasma etching processing and a resist application process, but they cannot explain all causes of the charge-up. One way or another, the charge-up in concern comes from charges caused by fixed charges that remain even when the sample is grounded. If such charge-up exists, a trajectory of the charged particle to be incident on the sample will be changed, and a focusing position of the incident electron beam will be shifted from the surface of the sample. As a result, a focusing position is shifted, which requires a time for adjusting the focusing position, causing throughput to be reduced. Moreover, when the above-mentioned amount of charge-up has an in-plane distribution, each time the position at which the measurement is conducted on a sample moves, the focusing adjustment as described above becomes necessary.
Against such problems, PCT International Publication WO 2003/007330 discloses the following technique. First, a wafer is taken out from a wafer cassette that carries wafers by a mechanical arm for wafer transportation of an atmosphere-side robot, and is transported to a load lock chamber. When the wafer is transported to this load lock chamber, a surface potential of the wafer is measured with a probe. Since in often cases, the wafer is charged up in the form of concentric circles, if a part of the probe that measures the surface potential traces on a straight line passing through the wafer center, a rough potential distribution on the whole surface of the sample will be able to be grasped.
Therefore, it becomes possible to correct focusing by measuring the surface potential of the sample beforehand with the above-mentioned probe before the measurement of dimensions of the fine pattern, and feeding back the value to the retarding voltage.